California State University, Northridge » Computer » Computer 222 - Computer Organization » Fall 2021

Computer 222 - Computer Organization » Fall 2021 » Midterm Exam

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Question #1

MIPS instruction: lw $r1,($r2) can address how much memory:

A. 1 GB

B. 2 MB

C. 32 MiB

D. 4 GiB

Question #2

A MIPS “I-format” immediate value as a signed constant can range from 0 to:

A. -32,768 to 32,767

B. -256 to 255

C. -65,565 to 65,564

D. -16,383 to 16,384

Question #3

An ARMv7 “I-format” immediate value as an unsigned constant can range from 0 to:

A. 4095

B. 1023

C. 224

D. 16,384

Question #4

ARMv7 primitives that MIPS does not have:

A. syscall, lui

B. push, bkpt, dbg

C. call, jump

D. addi, subi

Question #5

MIPS primitives that ARMv7 does not have:

A. beq, bgtz

B. syscall, break, lui

C. addi, subi

D. mult, div

Question #6

Currenty used ISA’s include these:

A. MIPSIII, ARMv5, IA-32, RISC V

B. MIPS32, ARMv6, x86-32, RISC III

C. MIPS64, ARMv8, IA-32, RISC V

D. MIPSV, ARMv7, x86-64, RISC IV

Question #7

A CPU core contains which blocks:

A. Execution Unit + L1 caches

B. L1 caches + Registers

C. ALU + Registers

D. ALU + L2 cache

Question #8

An x86 CPU, 32-bit contains:

A. SI, DI, CS, SS registers

B. EAX, EBX, ECX, EDX registers, SI, DI, CS, SS registers, and 32-bit ALU

C. 32-bit ALU

D. EAX, EBX, ECX, EDX registers

Question #9

x86 is what kind of architecture:

A. Mixed register

B. Dedicated register

C. Load-Store

D. General register

Question #10

A MIPS CPU core may contain an Integer unit + any of these, except which one:

A. up to 4 co-processors

B. GPU

C. CP0 + CP1

D. FPU

Question #11

For MIPS, where are the C, V, N, Z flags located:

A. CPU Cause register

B. CP1 $f2

C. CP0 Status register

D. CPU GR

Question #12

Which register is not a GR in MIPS, but is a GR in ARMv5:

A. SP

B. $a0

C. PC

D. PSR

Question #13

CPU General Registers are loaded directly from:

A. L1 I-cache

B. L1 D-cache

C. L3 cache

D. L2 cache

Question #14

A CPU’s store word instruction will write a data word to (with write-though policy):

A. L2 cache

B. Main memory

C. L1 D-cache

D. Main memory, L1 D-cache, and L2 cache

Question #15

In general, any level cache may use which form of mapping:

A. Set associative

B. Any of these

C. Direct

D. Fully associative

Question #16

R-format is used for which MIPS instruction:

A. addi

B. subi

C. add

D. bgtz

Question #17

I-format is used for which MIPS instruction:

A. addu

B. jal

C. div

D. lui

Question #18

J-format is used for which MIPS instruction:

A. bne

B. jal

C. addi

D. la

Question #19

At the Macro architecture level, we address all of which units:

A. Cores and caches

B. ICU + ALU + Registers

C. Just GPU’s

D. Just CPU cores

Question #20

CPU’s Execution Unit contains all these:

A. ICU + PSW

B. ALU + registers

C. CPU + GPU

D. ALU + ICU + registers

Question #21

An SoC (like the Apple A13/14) can contain which functional elements:

A. NPU cores + ML unit

B. L1 and L2 caches

C. Any of these

D. CPU + GPU cores

Question #22

Which {MIPS, ARM} add instructions should be used for unsigned integers:

A. add, adds

B. addu, addu

C. addu, add

D. addi, add

Question #23

Multi-level memory hierarchy from fastest to slowest:

A. L1 cache to L2 cache to L1 cache

B. Disk to Main to L2 cache

C. Main to L2 cache to L1

D. General Registers to L1 cache to L2 cache

Question #24

Any PSW contains:

A. Flags, Status bits, and Interrupt enables

B. Interrupt enables

C. Flags

D. Status bits

Question #25

ARM v8 was redesigned from v7 to be more like:

A. Apple A12X

B. IA-64

C. MIPS

D. ARMv5

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