California State University, Northridge » Computer » Computer 222 - Computer Organization » Fall 2021

Computer 222 - Computer Organization » Fall 2021 » Midterm Exam

Need help with your exam preparation?

Existing Quiz Clients Login here

Question #1

MIPS instruction: lw $r1,($r2) can address how much memory:

A. 4 GiB

B. 1 GB

C. 32 MiB

D. 2 MB

Question #2

A MIPS “I-format” immediate value as a signed constant can range from 0 to:

A. -256 to 255

B. -16,383 to 16,384

C. -32,768 to 32,767

D. -65,565 to 65,564

Question #3

An ARMv7 “I-format” immediate value as an unsigned constant can range from 0 to:

A. 224

B. 16,384

C. 4095

D. 1023

Question #4

ARMv7 primitives that MIPS does not have:

A. syscall, lui

B. addi, subi

C. call, jump

D. push, bkpt, dbg

Question #5

MIPS primitives that ARMv7 does not have:

A. beq, bgtz

B. addi, subi

C. mult, div

D. syscall, break, lui

Question #6

Currenty used ISA’s include these:

A. MIPS64, ARMv8, IA-32, RISC V

B. MIPSIII, ARMv5, IA-32, RISC V

C. MIPS32, ARMv6, x86-32, RISC III

D. MIPSV, ARMv7, x86-64, RISC IV

Question #7

A CPU core contains which blocks:

A. ALU + Registers

B. ALU + L2 cache

C. Execution Unit + L1 caches

D. L1 caches + Registers

Question #8

An x86 CPU, 32-bit contains:

A. 32-bit ALU

B. EAX, EBX, ECX, EDX registers, SI, DI, CS, SS registers, and 32-bit ALU

C. SI, DI, CS, SS registers

D. EAX, EBX, ECX, EDX registers

Question #9

x86 is what kind of architecture:

A. Load-Store

B. Dedicated register

C. General register

D. Mixed register

Question #10

A MIPS CPU core may contain an Integer unit + any of these, except which one:

A. GPU

B. CP0 + CP1

C. FPU

D. up to 4 co-processors

Question #11

For MIPS, where are the C, V, N, Z flags located:

A. CPU Cause register

B. CP0 Status register

C. CP1 $f2

D. CPU GR

Question #12

Which register is not a GR in MIPS, but is a GR in ARMv5:

A. PSR

B. PC

C. SP

D. $a0

Question #13

CPU General Registers are loaded directly from:

A. L2 cache

B. L1 D-cache

C. L3 cache

D. L1 I-cache

Question #14

A CPU’s store word instruction will write a data word to (with write-though policy):

A. L1 D-cache

B. L2 cache

C. Main memory

D. Main memory, L1 D-cache, and L2 cache

Question #15

In general, any level cache may use which form of mapping:

A. Any of these

B. Set associative

C. Direct

D. Fully associative

Question #16

R-format is used for which MIPS instruction:

A. addi

B. bgtz

C. subi

D. add

Question #17

I-format is used for which MIPS instruction:

A. addu

B. jal

C. div

D. lui

Question #18

J-format is used for which MIPS instruction:

A. bne

B. la

C. jal

D. addi

Question #19

At the Macro architecture level, we address all of which units:

A. Cores and caches

B. ICU + ALU + Registers

C. Just GPU’s

D. Just CPU cores

Question #20

CPU’s Execution Unit contains all these:

A. CPU + GPU

B. ICU + PSW

C. ALU + registers

D. ALU + ICU + registers

Question #21

An SoC (like the Apple A13/14) can contain which functional elements:

A. NPU cores + ML unit

B. Any of these

C. L1 and L2 caches

D. CPU + GPU cores

Question #22

Which {MIPS, ARM} add instructions should be used for unsigned integers:

A. addu, add

B. add, adds

C. addu, addu

D. addi, add

Question #23

Multi-level memory hierarchy from fastest to slowest:

A. Disk to Main to L2 cache

B. Main to L2 cache to L1

C. L1 cache to L2 cache to L1 cache

D. General Registers to L1 cache to L2 cache

Question #24

Any PSW contains:

A. Flags

B. Interrupt enables

C. Status bits

D. Flags, Status bits, and Interrupt enables

Question #25

ARM v8 was redesigned from v7 to be more like:

A. ARMv5

B. IA-64

C. MIPS

D. Apple A12X

Need help with your exam preparation?

Existing Quiz Clients Login here