California State University, Northridge » Computer » Computer 222 - Computer Organization » Fall 2021

Computer 222 - Computer Organization » Fall 2021 » Midterm Exam

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Question #1

MIPS instruction: lw $r1,($r2) can address how much memory:

A. 1 GB

B. 32 MiB

C. 2 MB

D. 4 GiB

Question #2

A MIPS “I-format” immediate value as a signed constant can range from 0 to:

A. -16,383 to 16,384

B. -65,565 to 65,564

C. -256 to 255

D. -32,768 to 32,767

Question #3

An ARMv7 “I-format” immediate value as an unsigned constant can range from 0 to:

A. 4095

B. 1023

C. 224

D. 16,384

Question #4

ARMv7 primitives that MIPS does not have:

A. syscall, lui

B. addi, subi

C. push, bkpt, dbg

D. call, jump

Question #5

MIPS primitives that ARMv7 does not have:

A. addi, subi

B. mult, div

C. beq, bgtz

D. syscall, break, lui

Question #6

Currenty used ISA’s include these:

A. MIPS64, ARMv8, IA-32, RISC V

B. MIPSV, ARMv7, x86-64, RISC IV

C. MIPS32, ARMv6, x86-32, RISC III

D. MIPSIII, ARMv5, IA-32, RISC V

Question #7

A CPU core contains which blocks:

A. ALU + L2 cache

B. Execution Unit + L1 caches

C. ALU + Registers

D. L1 caches + Registers

Question #8

An x86 CPU, 32-bit contains:

A. EAX, EBX, ECX, EDX registers, SI, DI, CS, SS registers, and 32-bit ALU

B. 32-bit ALU

C. EAX, EBX, ECX, EDX registers

D. SI, DI, CS, SS registers

Question #9

x86 is what kind of architecture:

A. Dedicated register

B. General register

C. Mixed register

D. Load-Store

Question #10

A MIPS CPU core may contain an Integer unit + any of these, except which one:

A. CP0 + CP1

B. up to 4 co-processors

C. FPU

D. GPU

Question #11

For MIPS, where are the C, V, N, Z flags located:

A. CP1 $f2

B. CPU GR

C. CPU Cause register

D. CP0 Status register

Question #12

Which register is not a GR in MIPS, but is a GR in ARMv5:

A. $a0

B. PC

C. SP

D. PSR

Question #13

CPU General Registers are loaded directly from:

A. L1 D-cache

B. L3 cache

C. L2 cache

D. L1 I-cache

Question #14

A CPU’s store word instruction will write a data word to (with write-though policy):

A. Main memory, L1 D-cache, and L2 cache

B. L1 D-cache

C. L2 cache

D. Main memory

Question #15

In general, any level cache may use which form of mapping:

A. Fully associative

B. Any of these

C. Set associative

D. Direct

Question #16

R-format is used for which MIPS instruction:

A. bgtz

B. subi

C. add

D. addi

Question #17

I-format is used for which MIPS instruction:

A. addu

B. div

C. lui

D. jal

Question #18

J-format is used for which MIPS instruction:

A. la

B. bne

C. addi

D. jal

Question #19

At the Macro architecture level, we address all of which units:

A. Just CPU cores

B. Just GPU’s

C. Cores and caches

D. ICU + ALU + Registers

Question #20

CPU’s Execution Unit contains all these:

A. ICU + PSW

B. CPU + GPU

C. ALU + ICU + registers

D. ALU + registers

Question #21

An SoC (like the Apple A13/14) can contain which functional elements:

A. Any of these

B. CPU + GPU cores

C. NPU cores + ML unit

D. L1 and L2 caches

Question #22

Which {MIPS, ARM} add instructions should be used for unsigned integers:

A. addu, add

B. add, adds

C. addu, addu

D. addi, add

Question #23

Multi-level memory hierarchy from fastest to slowest:

A. General Registers to L1 cache to L2 cache

B. L1 cache to L2 cache to L1 cache

C. Main to L2 cache to L1

D. Disk to Main to L2 cache

Question #24

Any PSW contains:

A. Flags

B. Interrupt enables

C. Flags, Status bits, and Interrupt enables

D. Status bits

Question #25

ARM v8 was redesigned from v7 to be more like:

A. MIPS

B. IA-64

C. ARMv5

D. Apple A12X

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