California State University, Northridge » Computer » Computer 222 - Computer Organization » Fall 2021

Computer 222 - Computer Organization » Fall 2021 » Midterm Exam

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Question #1

MIPS instruction: lw $r1,($r2) can address how much memory:

A. 32 MiB

B. 4 GiB

C. 2 MB

D. 1 GB

Question #2

A MIPS “I-format” immediate value as a signed constant can range from 0 to:

A. -16,383 to 16,384

B. -32,768 to 32,767

C. -256 to 255

D. -65,565 to 65,564

Question #3

An ARMv7 “I-format” immediate value as an unsigned constant can range from 0 to:

A. 1023

B. 4095

C. 16,384

D. 224

Question #4

ARMv7 primitives that MIPS does not have:

A. addi, subi

B. syscall, lui

C. call, jump

D. push, bkpt, dbg

Question #5

MIPS primitives that ARMv7 does not have:

A. beq, bgtz

B. syscall, break, lui

C. mult, div

D. addi, subi

Question #6

Currenty used ISA’s include these:

A. MIPSV, ARMv7, x86-64, RISC IV

B. MIPSIII, ARMv5, IA-32, RISC V

C. MIPS64, ARMv8, IA-32, RISC V

D. MIPS32, ARMv6, x86-32, RISC III

Question #7

A CPU core contains which blocks:

A. ALU + L2 cache

B. ALU + Registers

C. Execution Unit + L1 caches

D. L1 caches + Registers

Question #8

An x86 CPU, 32-bit contains:

A. EAX, EBX, ECX, EDX registers, SI, DI, CS, SS registers, and 32-bit ALU

B. SI, DI, CS, SS registers

C. 32-bit ALU

D. EAX, EBX, ECX, EDX registers

Question #9

x86 is what kind of architecture:

A. Mixed register

B. Load-Store

C. Dedicated register

D. General register

Question #10

A MIPS CPU core may contain an Integer unit + any of these, except which one:

A. up to 4 co-processors

B. CP0 + CP1

C. FPU

D. GPU

Question #11

For MIPS, where are the C, V, N, Z flags located:

A. CP1 $f2

B. CPU Cause register

C. CP0 Status register

D. CPU GR

Question #12

Which register is not a GR in MIPS, but is a GR in ARMv5:

A. PSR

B. $a0

C. PC

D. SP

Question #13

CPU General Registers are loaded directly from:

A. L3 cache

B. L2 cache

C. L1 I-cache

D. L1 D-cache

Question #14

A CPU’s store word instruction will write a data word to (with write-though policy):

A. L2 cache

B. Main memory, L1 D-cache, and L2 cache

C. Main memory

D. L1 D-cache

Question #15

In general, any level cache may use which form of mapping:

A. Set associative

B. Direct

C. Fully associative

D. Any of these

Question #16

R-format is used for which MIPS instruction:

A. subi

B. addi

C. bgtz

D. add

Question #17

I-format is used for which MIPS instruction:

A. lui

B. div

C. jal

D. addu

Question #18

J-format is used for which MIPS instruction:

A. la

B. jal

C. bne

D. addi

Question #19

At the Macro architecture level, we address all of which units:

A. Just CPU cores

B. ICU + ALU + Registers

C. Cores and caches

D. Just GPU’s

Question #20

CPU’s Execution Unit contains all these:

A. ICU + PSW

B. ALU + registers

C. ALU + ICU + registers

D. CPU + GPU

Question #21

An SoC (like the Apple A13/14) can contain which functional elements:

A. Any of these

B. L1 and L2 caches

C. NPU cores + ML unit

D. CPU + GPU cores

Question #22

Which {MIPS, ARM} add instructions should be used for unsigned integers:

A. addu, add

B. addu, addu

C. add, adds

D. addi, add

Question #23

Multi-level memory hierarchy from fastest to slowest:

A. General Registers to L1 cache to L2 cache

B. Main to L2 cache to L1

C. Disk to Main to L2 cache

D. L1 cache to L2 cache to L1 cache

Question #24

Any PSW contains:

A. Interrupt enables

B. Flags, Status bits, and Interrupt enables

C. Status bits

D. Flags

Question #25

ARM v8 was redesigned from v7 to be more like:

A. MIPS

B. ARMv5

C. IA-64

D. Apple A12X

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