California State University, Northridge » Computer » Computer 222 - Computer Organization » Fall 2021

Computer 222 - Computer Organization » Fall 2021 » Midterm Exam

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Question #1

MIPS instruction: lw $r1,($r2) can address how much memory:

A. 32 MiB

B. 1 GB

C. 4 GiB

D. 2 MB

Question #2

A MIPS “I-format” immediate value as a signed constant can range from 0 to:

A. -32,768 to 32,767

B. -65,565 to 65,564

C. -16,383 to 16,384

D. -256 to 255

Question #3

An ARMv7 “I-format” immediate value as an unsigned constant can range from 0 to:

A. 4095

B. 1023

C. 224

D. 16,384

Question #4

ARMv7 primitives that MIPS does not have:

A. call, jump

B. syscall, lui

C. push, bkpt, dbg

D. addi, subi

Question #5

MIPS primitives that ARMv7 does not have:

A. syscall, break, lui

B. beq, bgtz

C. addi, subi

D. mult, div

Question #6

Currenty used ISA’s include these:

A. MIPSIII, ARMv5, IA-32, RISC V

B. MIPSV, ARMv7, x86-64, RISC IV

C. MIPS64, ARMv8, IA-32, RISC V

D. MIPS32, ARMv6, x86-32, RISC III

Question #7

A CPU core contains which blocks:

A. Execution Unit + L1 caches

B. ALU + L2 cache

C. ALU + Registers

D. L1 caches + Registers

Question #8

An x86 CPU, 32-bit contains:

A. SI, DI, CS, SS registers

B. EAX, EBX, ECX, EDX registers, SI, DI, CS, SS registers, and 32-bit ALU

C. EAX, EBX, ECX, EDX registers

D. 32-bit ALU

Question #9

x86 is what kind of architecture:

A. General register

B. Load-Store

C. Mixed register

D. Dedicated register

Question #10

A MIPS CPU core may contain an Integer unit + any of these, except which one:

A. CP0 + CP1

B. FPU

C. up to 4 co-processors

D. GPU

Question #11

For MIPS, where are the C, V, N, Z flags located:

A. CP1 $f2

B. CPU GR

C. CP0 Status register

D. CPU Cause register

Question #12

Which register is not a GR in MIPS, but is a GR in ARMv5:

A. PSR

B. $a0

C. PC

D. SP

Question #13

CPU General Registers are loaded directly from:

A. L3 cache

B. L1 I-cache

C. L2 cache

D. L1 D-cache

Question #14

A CPU’s store word instruction will write a data word to (with write-though policy):

A. L1 D-cache

B. L2 cache

C. Main memory

D. Main memory, L1 D-cache, and L2 cache

Question #15

In general, any level cache may use which form of mapping:

A. Fully associative

B. Direct

C. Set associative

D. Any of these

Question #16

R-format is used for which MIPS instruction:

A. addi

B. add

C. subi

D. bgtz

Question #17

I-format is used for which MIPS instruction:

A. addu

B. jal

C. lui

D. div

Question #18

J-format is used for which MIPS instruction:

A. la

B. jal

C. bne

D. addi

Question #19

At the Macro architecture level, we address all of which units:

A. ICU + ALU + Registers

B. Just CPU cores

C. Just GPU’s

D. Cores and caches

Question #20

CPU’s Execution Unit contains all these:

A. ALU + registers

B. ALU + ICU + registers

C. ICU + PSW

D. CPU + GPU

Question #21

An SoC (like the Apple A13/14) can contain which functional elements:

A. CPU + GPU cores

B. NPU cores + ML unit

C. L1 and L2 caches

D. Any of these

Question #22

Which {MIPS, ARM} add instructions should be used for unsigned integers:

A. addi, add

B. add, adds

C. addu, add

D. addu, addu

Question #23

Multi-level memory hierarchy from fastest to slowest:

A. Disk to Main to L2 cache

B. L1 cache to L2 cache to L1 cache

C. General Registers to L1 cache to L2 cache

D. Main to L2 cache to L1

Question #24

Any PSW contains:

A. Status bits

B. Interrupt enables

C. Flags

D. Flags, Status bits, and Interrupt enables

Question #25

ARM v8 was redesigned from v7 to be more like:

A. IA-64

B. Apple A12X

C. MIPS

D. ARMv5

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