Computer 222 - Computer Organization » Fall 2021 » Quiz 1
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Question #1
16-bit CPU’s can directly address how much memory:
A.
64 KiB
B.
4 GiB
C.
64 GB
D.
16 KB
Question #2
32-bit CPU’s can directly address how much memory:
A.
2 MB
B.
4 GiB
C.
3200 KB
D.
1 GB
Question #3
210 exactly = in hexadecimal:
A.
0x0400
B.
0x0210
C.
0x100
D.
0x1000
Question #4
“Hell” is stored in memory in Little Endian (MIPS default) as:
A.
0x6c6c6a4a
B.
lleH (ASCII)
C.
0xff6c496c
D.
Hell (ASCII)
Question #5
Static data is stored in which memory segment:
A.
text
B.
heap
C.
data
D.
stack
Question #6
Dynamic data is stored in which memory segment:
A.
stack
B.
text
C.
data
D.
heap
Question #7
I/O is addressed in which memory segment:
A.
stack
B.
heap
C.
MMIO
D.
IO
Question #8
In a General Register CPU, R-format instructions address how many registers:
A.
0
B.
3
C.
1
D.
2
Question #9
In any CPU, which register holds a pointer to the top of the stack:
A.
GP
B.
PC
C.
FP
D.
SP
Question #10
At the Macro architecture level, we address all of which units:
A.
Cores and caches
B.
MLM
C.
GPU's
D.
CPU cores
Question #11
At the Micro architecture level, we address which functions:
A.
ICU
B.
Branch prediction
C.
Pipelines
D.
Cores
Question #12
Which is NOT a defined level of Computer Architecture in the stack model:
A.
Shared L2 cache
B.
Micro-architecture
C.
Macro-architecture
D.
ISA
Question #13
A MIPS CPU architecture provides for a main integer processor, plus:
A.
Dedicated registers
B.
Up to 4 GPU’s
C.
Up to 4 Program Counters
D.
Up to 4 co-processors, including an FPU
Question #14
The C, V, N, Z flags are all always updated by which one of these instructions:
A.
add
B.
ror
C.
ori
D.
and
Question #15
The “Program Counter” is stored in which Registers in MIPS, ARMv5:
A.
PC, R15
B.
$15, R14
C.
$sp, R0
D.
$0, R15
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