California State University, Northridge » Computer » Computer 222 - Computer Organization » Fall 2021 » Quiz 3 MIP Signed Arithmetic Conditional RISC V

Computer 222 - Computer Organization » Fall 2021 » Quiz 3 MIP Signed Arithmetic Conditional RISC V

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Question #1

Which MIPS add instructions should be used for unsigned integers:

A. add

B. add, addi

C. addi

D. addu, addiu

Question #2

The 2’s complement of the binary integer 2 is:

A. 111..10

B. 110..00

C. 111..00

D. 111..11

Question #3

Which arithmetic instruction takes more than 1 clock cycle:

A. Multiply

B. Shift

C. Subtract

D. Add

Question #4

Conditional constructs can be implemented in assembly via these instructions:

A. balr, bgl

B. br, bal

C. bne, beq, bgtz

D. jal, jalr

Question #5

Loop constructs can be implemented in assembly via these instructions:

A. bal Exit

B. bgtz Loop

C. br Loop

D. bl Loop

Question #6

Conditional constructs for >0 can be implemented in MIPS assembly via these instructions:

A. b, bal

B. bez, bnez

C. blt, bltz

D. bgtz, bgtzal

Question #7

Java code if(x<=0) y = 1; in MIPS assembly, with {x,y} in {$t1,$t2}, could be:

A. blez $t2, next; li $t2,1; next:

B. bgtz $t2, next; li $t1,1; next:

C. blez $t1, next; li $t2,1; next:

D. bgtz $t1, next; li $t2,1; next:

Question #8

RISC V is an open source CPU design based on which ISA

A. x86

B. AMD

C. MIPS

D. ARM

Question #9

RISC V differs from other ISA’s by this:

A. Including a 64-bit ISA

B. Uniform length instructions

C. Variable length instructions

D. Including a 16-bit ISA

Question #10

RISC V differs from other ISA’s by length of its opcode:

A. 6-bit

B. 8-bit

C. 5-bit

D. 7-bit

Question #11

RISC V differs from other ISA’s by placement of its opcode field:

A. Most-significant end

B. Least-significant end

C. 2nd byte

D. 3rd byte

Question #12

RISC V has how many GR’s:

A. 48

B. 64

C. 16

D. 32

Question #13

RISC V has which base instruction formats:

A. R, I, J

B. R, I, S, U

C. R, I

D. R, I, A, J

Question #14

RISC V accesses data memory via:

A. Load & Store using different instruction formats

B. Load & Store using same instruction formats

C. Move using I instruction format

D. Move using either R or I instruction format

Question #15

RISC V conditional branches support what type of comparison

A. Compare instruction to set flags first

B. 1 register to 0 (e.g.: $1 = 0)

C. 2 registers (to each other, e.g.: $1 = $2)

D. Any of these

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