California State University, Northridge » Computer » Computer 222 - Computer Organization » Fall 2021 » Quiz 3 MIP Signed Arithmetic Conditional RISC V

Computer 222 - Computer Organization » Fall 2021 » Quiz 3 MIP Signed Arithmetic Conditional RISC V

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Question #1

Which MIPS add instructions should be used for unsigned integers:

A. addu, addiu

B. addi

C. add, addi

D. add

Question #2

The 2’s complement of the binary integer 2 is:

A. 110..00

B. 111..10

C. 111..00

D. 111..11

Question #3

Which arithmetic instruction takes more than 1 clock cycle:

A. Shift

B. Add

C. Multiply

D. Subtract

Question #4

Conditional constructs can be implemented in assembly via these instructions:

A. jal, jalr

B. br, bal

C. bne, beq, bgtz

D. balr, bgl

Question #5

Loop constructs can be implemented in assembly via these instructions:

A. bgtz Loop

B. bal Exit

C. bl Loop

D. br Loop

Question #6

Conditional constructs for >0 can be implemented in MIPS assembly via these instructions:

A. bez, bnez

B. blt, bltz

C. b, bal

D. bgtz, bgtzal

Question #7

Java code if(x<=0) y = 1; in MIPS assembly, with {x,y} in {$t1,$t2}, could be:

A. blez $t1, next; li $t2,1; next:

B. blez $t2, next; li $t2,1; next:

C. bgtz $t1, next; li $t2,1; next:

D. bgtz $t2, next; li $t1,1; next:

Question #8

RISC V is an open source CPU design based on which ISA

A. AMD

B. ARM

C. x86

D. MIPS

Question #9

RISC V differs from other ISA’s by this:

A. Including a 64-bit ISA

B. Uniform length instructions

C. Including a 16-bit ISA

D. Variable length instructions

Question #10

RISC V differs from other ISA’s by length of its opcode:

A. 6-bit

B. 5-bit

C. 8-bit

D. 7-bit

Question #11

RISC V differs from other ISA’s by placement of its opcode field:

A. Most-significant end

B. 2nd byte

C. Least-significant end

D. 3rd byte

Question #12

RISC V has how many GR’s:

A. 32

B. 16

C. 48

D. 64

Question #13

RISC V has which base instruction formats:

A. R, I

B. R, I, J

C. R, I, A, J

D. R, I, S, U

Question #14

RISC V accesses data memory via:

A. Load & Store using different instruction formats

B. Load & Store using same instruction formats

C. Move using I instruction format

D. Move using either R or I instruction format

Question #15

RISC V conditional branches support what type of comparison

A. 2 registers (to each other, e.g.: $1 = $2)

B. 1 register to 0 (e.g.: $1 = 0)

C. Any of these

D. Compare instruction to set flags first

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