Computer 222 - Computer Organization » Fall 2021 » Quiz 3 MIP Signed Arithmetic Conditional RISC V

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Question #1
Which MIPS add instructions should be used for unsigned integers:
A.   addu, addiu
B.   add, addi
C.   add
D.   addi
Question #2
The 2’s complement of the binary integer 2 is:
A.   111..11
B.   111..00
C.   111..10
D.   110..00
Question #3
Which arithmetic instruction takes more than 1 clock cycle:
A.   Shift
B.   Multiply
C.   Add
D.   Subtract
Question #4
Conditional constructs can be implemented in assembly via these instructions:
A.   jal, jalr
B.   br, bal
C.   bne, beq, bgtz
D.   balr, bgl
Question #5
Loop constructs can be implemented in assembly via these instructions:
A.   bl Loop
B.   br Loop
C.   bgtz Loop
D.   bal Exit
Question #6
Conditional constructs for >0 can be implemented in MIPS assembly via these instructions:
A.   bez, bnez
B.   bgtz, bgtzal
C.   b, bal
D.   blt, bltz
Question #7
Java code if(x<=0) y = 1; in MIPS assembly, with {x,y} in {$t1,$t2}, could be:
A.   blez $t2, next; li $t2,1; next:
B.   bgtz $t2, next; li $t1,1; next:
C.   bgtz $t1, next; li $t2,1; next:
D.   blez $t1, next; li $t2,1; next:
Question #8
RISC V is an open source CPU design based on which ISA
A.   MIPS
B.   ARM
C.   AMD
D.   x86
Question #9
RISC V differs from other ISA’s by this:
A.   Including a 16-bit ISA
B.   Uniform length instructions
C.   Including a 64-bit ISA
D.   Variable length instructions
Question #10
RISC V differs from other ISA’s by length of its opcode:
A.   5-bit
B.   8-bit
C.   7-bit
D.   6-bit
Question #11
RISC V differs from other ISA’s by placement of its opcode field:
A.   Most-significant end
B.   3rd byte
C.   Least-significant end
D.   2nd byte
Question #12
RISC V has how many GR’s:
A.   64
B.   16
C.   32
D.   48
Question #13
RISC V has which base instruction formats:
A.   R, I, J
B.   R, I, A, J
C.   R, I
D.   R, I, S, U
Question #14
RISC V accesses data memory via:
A.   Move using I instruction format
B.   Move using either R or I instruction format
C.   Load & Store using different instruction formats
D.   Load & Store using same instruction formats
Question #15
RISC V conditional branches support what type of comparison
A.   1 register to 0 (e.g.: $1 = 0)
B.   Any of these
C.   2 registers (to each other, e.g.: $1 = $2)
D.   Compare instruction to set flags first

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