Computer 222 - Computer Organization » Fall 2021 » Quiz 2 Computer Org MIPS
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Question #1
CPU’s Execution Unit contains all these:
A.
ALU + registers
B.
ICU + PSW
C.
CPU + GPU
D.
ALU + ICU + registers
Question #2
A CPU core contains which blocks:
A.
Execution Unit + L1 caches
B.
L1 caches + Registers
C.
ALU + L2 cache
D.
ALU + Registers
Question #3
An SoC can contain which functional elements:
A.
FPU
B.
CPU
C.
Any of these
D.
GPU
Question #4
MIPS32 ISA contains:
A.
Integer square-root
B.
Integer and FPU primitives + pseudo ops
C.
pseudo ops + macros
D.
Integer + FPU directives
Question #5
A MIPS CPU may contain an Integer unit + any of these, except which one:
A.
CP0 + CP1
B.
GPU
C.
FPU
D.
up to 4 co-processors
Question #6
MIPS CP0 contains which set of registers:
A.
BadVA + Status + Cause + EPC
B.
PC+RA
C.
FPU + EPC
D.
PSW + PC
Question #7
MIPS CP1 contains which set of registers:
A.
$f0 - $f31
B.
$f0 - $g15
C.
PC, RA, SP, FP
D.
$0 - $31
Question #8
MIPS CP2 contains which set of registers:
A.
TBD (not defined)
B.
$0 - $31
C.
$f0 - $f15
D.
PC, RA, SP, FP
Question #9
MIPS FPU is also called:
A.
TBD (not defined)
B.
$f0 - $f31
C.
PSW
D.
CP1
Question #10
MIPS FPU has these instructions in its ISA, except which
A.
addi
B.
mfc1
C.
add.s
D.
sub.d
Question #11
MIPS “Load” instructions can read data from which memory segments:
A.
stack
B.
heap
C.
data, stack and heap
D.
data
Question #12
MIPS “Store” instructions first write data via a “Write Buffer” directly into where:
A.
Main memory
B.
L1 I-cache
C.
L2 cache
D.
L1 D-cache
Question #13
MIPS32 “Load Immediate” (“li”) and “Load Address” (“la”) instructions are what kind of instructions:
A.
macro
B.
primitive
C.
pseudo
D.
none of these
Question #14
MIPS32 lw, lh, lhu, lb, lbu instructions are what kind of instructions:
A.
none of these
B.
pseudo
C.
primitive
D.
macro
Question #15
In MIPS32, execution of this code results in data being stored into which memory segment: li $t2,0x100400a sb $t1,($t2)
A.
heap
B.
data
C.
stack
D.
global
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