Computer 222 - Computer Organization » Fall 2021 » Quiz 2 Computer Org MIPS
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Question #1
CPU’s Execution Unit contains all these:
A.
CPU + GPU
B.
ALU + ICU + registers
C.
ICU + PSW
D.
ALU + registers
Question #2
A CPU core contains which blocks:
A.
ALU + L2 cache
B.
Execution Unit + L1 caches
C.
ALU + Registers
D.
L1 caches + Registers
Question #3
An SoC can contain which functional elements:
A.
CPU
B.
GPU
C.
Any of these
D.
FPU
Question #4
MIPS32 ISA contains:
A.
Integer + FPU directives
B.
Integer and FPU primitives + pseudo ops
C.
Integer square-root
D.
pseudo ops + macros
Question #5
A MIPS CPU may contain an Integer unit + any of these, except which one:
A.
up to 4 co-processors
B.
CP0 + CP1
C.
FPU
D.
GPU
Question #6
MIPS CP0 contains which set of registers:
A.
BadVA + Status + Cause + EPC
B.
PSW + PC
C.
PC+RA
D.
FPU + EPC
Question #7
MIPS CP1 contains which set of registers:
A.
$f0 - $g15
B.
PC, RA, SP, FP
C.
$0 - $31
D.
$f0 - $f31
Question #8
MIPS CP2 contains which set of registers:
A.
TBD (not defined)
B.
$f0 - $f15
C.
PC, RA, SP, FP
D.
$0 - $31
Question #9
MIPS FPU is also called:
A.
TBD (not defined)
B.
$f0 - $f31
C.
PSW
D.
CP1
Question #10
MIPS FPU has these instructions in its ISA, except which
A.
addi
B.
add.s
C.
mfc1
D.
sub.d
Question #11
MIPS “Load” instructions can read data from which memory segments:
A.
heap
B.
data
C.
data, stack and heap
D.
stack
Question #12
MIPS “Store” instructions first write data via a “Write Buffer” directly into where:
A.
L1 I-cache
B.
Main memory
C.
L1 D-cache
D.
L2 cache
Question #13
MIPS32 “Load Immediate” (“li”) and “Load Address” (“la”) instructions are what kind of instructions:
A.
macro
B.
none of these
C.
primitive
D.
pseudo
Question #14
MIPS32 lw, lh, lhu, lb, lbu instructions are what kind of instructions:
A.
pseudo
B.
none of these
C.
primitive
D.
macro
Question #15
In MIPS32, execution of this code results in data being stored into which memory segment: li $t2,0x100400a sb $t1,($t2)
A.
data
B.
global
C.
stack
D.
heap
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