Computer 222 - Computer Organization » Fall 2021 » Quiz 6 Interrupts PSW Registers
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Question #1
Interrupts have all these properties, except:
A.
Cause no pipeline flush
B.
A sub-class of Exception
C.
Priority
D.
Preemption
Question #2
Low priority devices should use what class of Interrupt:
A.
Vectored
B.
Non-Vectored
C.
NMI
D.
Maskable
Question #3
What is an Interrupt Vector:
A.
A byte used by an ISR to decode the identity of an interrupting device
B.
A byte provided by an interrupting device to identify itself
C.
A byte that can be used by an ISR as a branch target offset, a byte provided by an interrupting device to identify itself, and a byte used by an ISR to decode the identity of an interrupting device
D.
A byte that can be used by an ISR as a branch target offset
Question #4
Interrupts are processed if what conditions are met:
A.
Mask and global enable bits are set, it is pending and highest priority
B.
Vectored with vector present on data bus
C.
Enabled and pre-emptive
D.
Pending and maskable
Question #5
PSW contains:
A.
Process Software
B.
Program Software
C.
Program Status Word
D.
Priority Sequence Word
Question #6
MIPS PSW contains:
A.
Interrupt enables, Status register, and Flags
B.
Interrupt enables
C.
Flags
D.
Status register
Question #7
MIPS CP0 contains a Cause register, which contains:
A.
Endianness control
B.
Interrupt enables
C.
Exception code + interrupts pending
D.
Exception code only
Question #8
MIPS CP0 contains which registers:
A.
Cause + Status
B.
EPC + Count
C.
BadVAddr + Config, EPC + Count, and Cause + Status
D.
BadVAddr + Config
Question #9
Registers are composed of a linear array of what logic element:
A.
NAND gates
B.
RS latches
C.
D flip-flops
D.
ALU
Question #10
Which sequential logic element is clock-edge triggered:
A.
ALU
B.
Latches
C.
Flip-flops
D.
NAND gates
Question #11
Which clocking scheme helps keep a digital system tightly synchronized (even used in the i8080):
A.
Single-phase clocking
B.
Falling-edge clocking
C.
Rising-edge clocking
D.
2-phase clocking
Question #12
What type of logic block is necessary for an FSM – Finite State Machine:
A.
Latches
B.
Decoders
C.
Registers
D.
ALU
Question #13
What type of analog circuit is necessary for providing a stable clock:
A.
ALU
B.
Inductors
C.
PLL, including a VCXO
D.
D flip-flops
Question #14
What is used to distribute a system clock to all of the system:
A.
PLL tree
B.
Quartz crystal
C.
Control bus
D.
Registers
Question #15
A stable system clock will help keep any digital system:
A.
Synchronized
B.
Asynchronous
C.
Indifferent
D.
Clocked
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